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6 nm · Bulk FinFET, EUV BEOL

LM06FF-H

6 nm FinFET, high performance

Status

Technology description complete; device models fitted; libraries next.

The five kits at the same scale: LM06FF-H's four fins
The five kits at the same scale: LM06FF-H's four fins

LM06FF-H is a 7/6 nm-class high-performance FinFET kit with an extreme-ultraviolet (EUV) patterned interconnect. Its front-end dimensions (54 nm gate pitch, 27 nm fin pitch) follow the well-known ASAP7 predictive research kit; its transistor targets, models, interconnect and libraries are our own, each cited.

Why 6 nm

The 7/6 nm class is where high-performance computing, mobile processors and AI accelerators moved in volume, and where interconnect resistance and transistor variability became first-order design problems. It is the last FinFET generation in our family before the move to gate-all-around.

Technology at a glance

Supply0.7 V nominal
Contacted gate pitch54 nm
Gate length21 nm
Fin pitch / height / width27 / 32 / 6.5 nm
Metal stack10 layers, 36 nm minimum pitch
Cell heights6 and 7.5 tracks
Threshold voltagesSLVT, LVT, RVT, plus SRAM devices
Device modelBSIM-CMG

Transistors

DeviceLeakage (nA/µm)Drive (µA/µm)
nMOS SLVT / LVT / RVT90 / 9 / 0.71881 / 1674 / 1402
pMOS SLVT / LVT / RVT89 / 8.5 / 0.851718 / 1500 / 1226

Currents are per micrometre of layout width.

Id–Vg of all eight fitted devices
Id–Vg of all eight fitted devices

Interconnect

At 36 nm pitch, copper lines are only 18 nm wide, and their resistance is about 95 Ω per micrometre, roughly 17 times that of the 40 nm kit's narrowest wires. Our stack models that size effect layer by layer, and self-forming barriers that lower via resistance.

The stack to scale
The stack to scale
Resistance and capacitance per metal layer
Resistance and capacitance per metal layer

At 6 nm, random variation between neighbouring transistors and the rising resistance of very narrow wires dominate timing. We will build statistical timing libraries and size-effect-aware wire models, and show which paths are limited by wires rather than by gates.

Built from

The ASAP7 research kit (front-end rules and device targets), the IRDS roadmap, and published studies of copper resistivity at nanometre widths.

Next

Standard-cell libraries at two heights and three threshold flavours, then characterization.

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