One register description. RTL, UVM model, C header and docs from it.
Lumina Reg reads your registers from SystemRDL 2.0 or IP-XACT, writes everything the design and verification flow needs from one model, and checks the model for what cannot be built, before any of it reaches RTL.
Options from the Lumina Reg command line
- SystemRDL 2.0
- Accellera
- IEEE 1685-2022
- IP-XACT, also 2014 and 2009
- RTL · UVM · C · docs
- from one model
- Register lint
- before RTL
What Lumina Reg does
SystemRDL 2.0
The full grammar and its preprocessor, parameters, enums, structs, user-defined properties, field and address allocation, aliases and memories, with the standard's semantic rules.
IP-XACT
IEEE 1685-2022, 2014 and 2009 components: memory maps, address blocks, register files, registers and fields with their access, side effects, resets and enumerated values.
SystemVerilog register block
A CSR slave on a simple request and response bus, hardware interface structs, the software and hardware access semantics, counters and interrupts.
UVM register model
uvm_reg_block, uvm_reg, uvm_reg_field and uvm_mem classes, address maps and backdoor HDL paths, run on Lumina Sim with UVM's register test sequences.
C header
Addresses, field masks and shifts, and reset values, for firmware and drivers.
Documentation and export
HTML and Markdown register documentation, and IP-XACT export from SystemRDL.
Register lint
Overlapping registers or fields, fields outside their register, resets wider than their field, access that cannot be built, unaligned addresses and names invalid in the generated languages.
One set of diagnostics
Register findings report and waive through the same system as Lumina Lint, and the generated RTL is linted like the rest.
Outputs
- SystemVerilog
Register block with a CSR bus slave, hardware structs, access semantics, counters and interrupts
- UVM
IEEE 1800.2 register model with maps and backdoor HDL paths
- C
Header with addresses, field masks and shifts, reset values
- HTML · Markdown
Register documentation
- IP-XACT
IEEE 1685-2022 export of a SystemRDL model
Frequently asked
What is SystemRDL?
The Accellera language for describing registers and memory maps. One description is the source for the RTL, the verification model, the software headers and the documentation, so they cannot drift apart.
Can I convert SystemRDL to IP-XACT?
Yes. Lumina Reg exports an IEEE 1685-2022 IP-XACT component from a SystemRDL model, and reads IP-XACT back into the same model.
Does the UVM register model run on other simulators?
It is standard IEEE 1800.2 code built from uvm_reg classes, so it runs wherever UVM does. It is tested on Lumina Sim with UVM's built-in register sequences.
Run your own design on Lumina first.
We are working with a small group of design teams before release. You run your real designs; we fix what you find, and your cases become part of the tests every build must pass.