Clock domain crossings found, explained and checked against your constraints.
Lumina CDC traces every flop's clock and asynchronous reset back to where it comes from and follows the data between flops. It recognises synchronizers, explains every crossing it cannot show safe, and checks your SDC or XDC against the design it constrains. No constraint file is needed to start.
Commands from the clock and reset domain guide
- CDC · RDC
- one analysis
- SDC · XDC
- read, checked and written
- Checked
- constraints against the RTL
- JSON
- clocks and crossings for your tools
What Lumina CDC checks
Synchronizers recognised
Two-flop synchronizers, shift registers and synchronizer cells are found from the structure. Each crossing bit is classified as synchronized, logic before a synchronizer, qualified by a handshake, or unsynchronized.
Multi-bit crossings
A bus synchronized bit by bit is reported, unless its source register is Gray-coded.
Reset domain crossings
Resets de-asserted asynchronously to their flop's clock, single-stage reset synchronizers, and data from flops whose reset does not also reset the destination.
Constraints checked against the RTL
Objects that match nothing, clocks never defined, generated clocks with the wrong source, ports with no delay, and clock groups or false paths that hide an unsynchronized crossing.
Constraints written from the design
A starting SDC or XDC: create_clock, generated clocks, set_max_delay -datapath_only or asynchronous clock groups for each crossing, each command with a comment saying why.
Proved by formal
A crossing the analysis flags is one Lumina Formal can prove safe or show failing, and multicycle paths are proved rather than assumed.
Tell it what structure cannot show
Synchronous clock groups, quasi-static configuration registers, resets that assert together, reset ordering and isolation signals.
Design data for your tools
The clocks, crossings, state machines and netlist written as versioned JSON, for scripts, dashboards and AI agents.
How each crossing is classified
- Synchronized
Comes from the other domain through wires only, into the first stage of a synchronizer
- Logic before a synchronizer
The same, but with logic between the source and the synchronizer: reported
- Qualified
Guarded by a synchronized handshake or FIFO control
- Unsynchronized
Anything else: reported, with the path that crosses
- Multi-bit
A bus synchronized bit by bit from a register that is not Gray-coded: reported
The constraint file checked against the design
- Objects
Ports, cells, pins or nets in the file that match nothing in the design
- Clocks
Clocks the design has and the file does not define, or defines wrongly
- I/O delays
Inputs and outputs left without a delay
- Exceptions
Clock groups or false paths that hide an unsafe crossing, or crossings no exception covers
Frequently asked
What is a clock domain crossing?
A signal launched by a flop on one clock and captured by a flop on another, unrelated clock. Without a synchronizer the capturing flop can go metastable, and the bug may only appear in silicon, rarely and at random. CDC analysis finds these paths in the RTL, before they cost a respin.
What is a reset domain crossing?
Data that moves between flops reset by different resets, or a reset released without regard to the clock of the flops it resets. When one reset asserts while the other domain keeps running, the destination can capture a value in the middle of changing.
Do I need a constraint file to start?
No. Without one every clock is its own domain unless you declare it synchronous, so you see every crossing. Add your SDC or XDC with --sdc to relate the clocks as timing analysis does and to check the file itself.
Does it work for FPGA designs?
Yes. It reads the SDC commands of XDC files, writes XDC, and the FPGA rule pack adds checks for the fabric's clock and reset structure.
Run your own design on Lumina first.
We are working with a small group of design teams before release. You run your real designs; we fix what you find, and your cases become part of the tests every build must pass.