The Lumina system
Debug · Lumina Sim

Step through RTL like software. Find the cause, not just the failure.

Lumina Sim stops at a line, steps through processes, prints and forces signals, and watches them change, on the terminal or in your editor through the Debug Adapter Protocol. Waveforms are written as FST or VCD, and a long run can be saved at any time and started again from there.

lumsim --debugCONNECTED
$ lumsim tb.sv --top tb --debug
# the run stops before time 0 and takes commands
break rtl/fifo.sv:42 if full
continue
print tb.dut.u_fifo.count
watch tb.dut.u_fifo.wr_ptr
force tb.dut.stall 1
run 100ns

Debugger commands from the Lumina Sim guide

DAP
VS Code and other editors
FST · VCD
waveforms
Conditional
breakpoints and watches
Checkpoints
restart mid-run
Capabilities

What you can do

A debugger on the terminal

Breakpoints with conditions, step, next and finish, print and deposit values, force and release, watches, and the list of processes and where each one is.

The same debugger in your editor

lumsim --dap is a Debug Adapter Protocol server: breakpoints with conditions and hit counts, stepping, the call stack, variables and watch expressions, in VS Code or any DAP editor.

Waveforms

FST and VCD, with $dumpvars scopes and depths, $dumpports extended VCD, and FST files several times smaller than VCD. Any FST or VCD viewer opens them.

Scriptable waves

lumwave prints a dump's hierarchy and any signal's values over a time window as JSON, for scripts and AI agents.

Assertion traces

Every failure printed with its location, time and message, even where the assertion's action block handles it.

Checkpoints

Run a long boot or reset sequence once, keep the state, and start each experiment from there with its own seed, plusargs and waveform file.

Planned

Waves and source in one view

The waves, the source with the values at the cursor time, and the hierarchy, in one editor window, with lint findings beside the signals they concern.

Planned

Drivers and loads

From a wrong value, step back to the process and the line that wrote it.

Reference

Debugger commands

  • break <file>:<line> [if <cond>]

    A breakpoint, with an optional condition on a signal

  • continue, run <time>

    Run on, or run for a time

  • step, next, finish

    One statement; one statement over calls; out of the current subroutine

  • print <path>

    A signal or variable

  • set <path> <value>

    Deposit a value, X included

  • force, release

    Force and release a signal

  • watch <path>...

    Stop when the signals change

  • info threads, info where, info locals

    The processes, where the current one is, its variables

Questions

Frequently asked

Can I set breakpoints in SystemVerilog code?

Yes, on any line, with an optional condition such as a signal being 1 or equal to a value. Execution stops there and you can step statement by statement, print and change values, and continue.

Does it work in VS Code?

Yes. lumsim --dap is a Debug Adapter Protocol server; with the Lumina extension a launch configuration starts the simulation under the debugger. Other editors with DAP support use the same server.

Which waveform formats are written?

FST and VCD, plus extended VCD from $dumpports. FST is several times smaller than VCD and faster to write.

What is a simulation checkpoint?

The full state of a run saved at a chosen time. Later runs restore it and continue with their own plusargs, seed and waveform file, so a long boot or reset sequence runs only once.

Run your own design on Lumina first.

We are working with a small group of design teams before release. You run your real designs; we fix what you find, and your cases become part of the tests every build must pass.

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