LM-TRNG is a physical random number generator IP core for FPGA and SoC designs.
The entropy source is an array of free-running ring oscillators, sampled by the system clock to harvest the thermal jitter in their periods. The digitised noise passes through a configurable parity filter and a continuous health-test chain before reaching the output, and the core inhibits output while any test is in alarm.
The core is delivered as vendor-neutral SystemVerilog and builds from one source on AMD, Altera and Efinix devices. It includes AMBA AXI interfaces and a register map, and ANSI C drivers are provided for fast integration into the target platform.
Measured FPGA results
Product top, out of context, constrained at the target clock. AMD and Efinix report LUTs, Altera reports ALMs; the two are never combined.
| Device | Configuration | Logic | FF | Memory | DSP | Fmax |
|---|---|---|---|---|---|---|
| Altera Agilex 3A3CW135BM16AE6S · quartus-pro 26.1.1 | APT_W_LOG2=10, AXIS_W=32, PFILT_MAX=128, ROSC_N=8, ROSC_STAGES=13, ROSC_TAPS=3, S22_W_LOG2=12, SRC_EXT=0 | 852 ALM | 1,469 | 0 Kb M20K | 3 | 295.2 MHztarget 295 |
| AMD Kintex UltraScale+xcku3p-ffva676-1-e · vivado 2026.1 | APT_W_LOG2=10, AXIS_W=32, PFILT_MAX=128, ROSC_N=8, ROSC_STAGES=13, ROSC_TAPS=3, S22_W_LOG2=12, SRC_EXT=0 | 968 LUT | 1,141 | 0 BRAM | 4 | 481.9 MHztarget 475 |
| Efinix Titanium Ti375Ti375N1156 · efinity 2026.1 | APT_W_LOG2=10, AXIS_W=32, PFILT_MAX=128, ROSC_N=8, ROSC_STAGES=13, ROSC_TAPS=3, S22_W_LOG2=12, SRC_EXT=0 | 1,107 LUT | 1,027 | 0 RAM | 6 | 457.5 MHztarget 400 |
Features
Entropy source
- Array of free-running inverter rings, configurable in count and length
- Every phase of every ring sampled and combined
- External noise source accepted instead, for a system supplying its own
Conditioning
- Configurable XOR parity filter with a length clamp
- One output bit per configured group of raw bits — no bit reused, none discarded
Continuous health tests
- Repetition Count Test — NIST SP 800-90B section 4.4.1
- Adaptive Proportion Test — NIST SP 800-90B section 4.4.2
- Total failure test — AIS-31 requirement PTG.2.5, watching for a stopped ring
- Frequency (monobit) and Runs tests — NIST SP 800-22 sections 2.1 and 2.3, applied continuously over configurable windows
- Power-up known-answer test of the deterministic path
- Output inhibited while any test is in alarm; every alarm latched and readable
Integration
- AMBA AXI4-Lite control and an AXI4-Stream random output
- All test thresholds are registers, so an integrator sets them from their own assessment
- Two delivery tops: complete AXI product, or bare core for a custom fabric
- ANSI C driver, UVM RAL, IP-XACT, SystemRDL register description
Applications
- Seeding a deterministic random bit generator — LM-DRBG is the matching block
- Key generation at power-up, before any seed exists
- Nonce and challenge generation
- Physical unclonable and device-identity schemes
- Any system requiring a non-deterministic source rather than a seeded one
Block diagram
Interfaces
| Interface | Type | Width | Carries |
|---|---|---|---|
s_axil | AXI4-Lite slave | 32-bit | capability, configuration, thresholds, status, alarms, counters |
m_axis | AXI4-Stream source | AXIS_W | the random output |
irq | level | 1-bit | alarm and status events |
The output stream has no end. A physical source produces bits for as long as it is
enabled; there is no request length and no tlast. That is the structural difference
from a deterministic generator, and it is visible at the interface.
Health and assurance
Four continuous tests plus a power-up self-test. The two SP 800-90B tests are implemented as the document writes them, including the boundary conditions each is easy to get wrong. The AIS-31 total-failure test watches the sampled ring phases directly rather than the combined noise bit, so a stopped ring is caught sooner and more specifically than a statistical test would catch it.
Every threshold is a register. Cutoffs, window sizes and the parity filter length are configuration, not constants, because an integrator validating this source on their own device and operating corner must be able to set them from their own assessment.
Output is inhibited while any test is in alarm, and every alarm is latched.
The entropy claim, stated plainly
The min-entropy per sample is not established by this deliverable, and no figure is claimed. A min-entropy estimate requires at least one million consecutive raw samples collected from the physical source on the target device at the operating corner, run through the SP 800-90B estimators. That is a measurement on hardware, and it cannot be produced by simulation, synthesis or any artefact in this package.
The default threshold values shipped in the register map are computed from an assumed min-entropy, and that assumption is labelled as one everywhere it appears. An integrator seeking any validation replaces every threshold from their own assessment — which is precisely why they are registers.
The ring oscillator array has no model and is not simulated. Everything downstream of the digitised noise bit is a deterministic state machine and is verified clock by clock against a reference model; the rings themselves are physical and are verified by measurement on silicon, which is the integrator's to perform.
Configuration
| Parameter | Type | Effect |
|---|---|---|
ROSC_N, ROSC_STAGES, ROSC_TAPS | elaboration | ring count, length, phases tapped |
SRC_EXT | elaboration | use an external noise source instead of the rings |
PFILT_MAX | elaboration | maximum parity-filter group length |
APT_W_LOG2, S22_W_LOG2 | elaboration | health-test window sizes |
AXIS_W | elaboration | output stream width |
| thresholds, cutoffs, filter length | run time | set from the integrator's own assessment |
Resources and performance
Resource utilisation and maximum clock frequency for each target device are measured out of context and published per target in the measured results on this page. AMD and Efinix rows report LUTs; Altera rows report ALMs, and the two are never combined.
Output rate is the sample rate divided by the parity filter length, and both are configuration.
Deliverables
| Item | Contents |
|---|---|
| RTL | parameterised SystemVerilog, vendor-neutral |
| Model | cycle-accurate C++ model of the deterministic path |
| Registers | SystemRDL source plus six generated exports |
| Verification | UVM RAL, formal property wrappers, health-test vector drivers |
| Software | ANSI C reference driver with generated header and JSON |
| Packaging | IP-XACT, IEEE 1685-2022 |
| Implementation | runnable flow script per FPGA vendor, file list, SDC |
| Documentation | integration guide |