SystemVerilog lint that reads the whole design.
Lumina Lint reads your design the way a simulator does, with file lists, include directories, defines and libraries, elaborates it, and reports what is wrong: bugs, synthesis problems, unsafe crossings and breaks of your team's conventions. Every finding has a stable rule ID, a severity, a location and the facts behind it.
Output format from the Lumina Lint guide
- Hundreds
- of rules
- Rule packs
- FPGA, ASIC and your own
- As you type
- in your editor
- SARIF · JSON
- for CI
What Lumina Lint does
The elaborated design, not file by file
Many findings depend on the hierarchy, the clocks and the connections. Width mismatches at ports, multiple drivers, latches and combinational loops are found across modules.
Rule packs
builtin:rtl-signoff raises synthesis, structural, reset and state machine rules to errors; builtin:fpga adds control-set and clock-structure checks for FPGA fabrics. Your company pack extends them.
Custom rules without code
Naming patterns, banned constructs, header text, size limits and design queries such as "flop where reset == ''", written in a TOML file.
Testbench rules too
Unchecked randomize(), UVM factory and configuration misuse, and testbench code kept apart from design code.
In your editor as you type
A Language Server Protocol server: findings on open, on pause and on save, the rule's description on hover, and a quick fix that waives in place.
Made for CI
Text, JSON, SARIF and HTML reports, byte-identical for the same input. A baseline lets an existing design fail only on new findings.
Clock and reset domains
CDC and RDC rules on the same netlist, and SDC or XDC files checked against the RTL. See Lumina CDC.
VHDL language rules
VHDL designs are checked for clocks, resets, crossings and structure through their RTL form today; VHDL's own language rules are planned.
What the rules cover
Every rule has a stable ID, a default severity and its own parameters, and can be turned on, off or raised to an error per project.
- Correctness
Width mismatches, signed and unsigned mixes, incomplete case, blocking and nonblocking misuse
- Structure
Latches, combinational loops, multiple drivers, undriven bits
- Synthesis
Constructs that simulate but do not build, such as delays and initial blocks in design code
- Clocks and resets
Gated and generated clocks, reset structure and polarity, unsafe crossings
- State machines
Unreachable states and states with no way out
- Testbench
Unchecked randomize() and UVM factory and configuration misuse
- Style and naming
Your team's naming patterns and coding conventions
- FPGA
Control sets and clock and reset structure for FPGA fabrics
Frequently asked
What is HDL lint?
Static analysis of Verilog, SystemVerilog or VHDL source. It finds bugs, synthesis problems and style issues without running a simulation, so they are fixed in minutes instead of being found in a regression or on the bench.
Can I add my own lint rules?
Yes, without writing code. Naming, construct, text, size and design-query rules are declared in a TOML file, shared in a rule pack, listed with the built-in rules and waived the same way.
How do I adopt lint on an existing design?
Run it once and keep the result as a baseline. From then on, only new findings fail the check, and the old ones can be worked through over time.
Which editors does it work in?
Any editor with Language Server Protocol support. VS Code has the Lumina extension, which also carries the Lumina Sim debugger.
Does Lumina Lint check FPGA designs?
Yes. The builtin:fpga pack turns on the rules for control sets and for reset and clock structure in the fabric, and the clock relations of XDC files are read.
Run your own design on Lumina first.
We are working with a small group of design teams before release. You run your real designs; we fix what you find, and your cases become part of the tests every build must pass.